€10-50M per call to build Europe's semiconductor and AI-chip stack — pilot lines, chip design, quantum, and skills
European Chips Act / Chips Joint Undertaking
Co-funded partnership: minority EU/Chips JU contribution (~20% large-enterprise IA to ~35% non-profit) plus national co-funding on top
What is Chips JU?
The Chips Joint Undertaking (Chips JU) is the EU's funding engine for semiconductors — the brains inside everything from cars to data centres to AI accelerators. It runs the "Chips for Europe Initiative," the technology arm of the European Chips Act, which channels up to €3.3 billion of EU money (€1.65 billion from Horizon Europe plus €1.65 billion from the Digital Europe Programme) into the research, pilot lines, design tools and skills Europe needs to stop importing nearly all its advanced chips. Counting matching national contributions and private investment, the Chips JU expects to mobilise close to €11 billion by 2030. Unlike the EIC, this is consortium-based, collaborative R&D: you apply with partners across several countries, not as a lone startup. The funding model matters: the Chips JU is a co-funded partnership, not a standard Horizon grant, so the EU/Chips JU slice is a minority co-funding contribution — roughly 20% of eligible costs for a large enterprise in an Innovation Action up to around 35% for a non-profit — and your own government's national co-funding makes up the rest of a viable total. Most calls fund Research and Innovation Actions (RIA, earlier-stage research at TRL 3-4) or Innovation Actions (IA, closer-to-market work at TRL 5-8). TRL means Technology Readiness Level, a 1-9 scale where 1 is a lab idea and 9 is a product in the field.
- Up to €3.3B EU budget (€1.65B Horizon Europe + €1.65B Digital Europe)
- Calls of €10-50M each across chip design, photonics, quantum, power electronics and skills
- Co-funded model: the EU/Chips JU grant is a minority slice (~20-35% of costs); national co-funding from your own government makes up the rest
- Funds pilot lines, a design platform, and 30 competence centres across 28 countries
- RIA at TRL 3-4 and IA at TRL 5-8
- Consortium-based — apply with partners across multiple countries
Is this for you?
This is built for organisations doing serious semiconductor R&D as part of a cross-border team: chipmakers and fabless designers, semiconductor-equipment and materials vendors, photonics and quantum hardware companies, research and technology organisations (RTOs like imec, CEA-Leti, Fraunhofer), and universities. If you have a real technical contribution to make to Europe's chip stack — advanced packaging, power electronics, photonic integration, chip-design tooling, quantum components or training the workforce — and partners in several countries to build it with, this is for you. If you are a lone founder looking for non-dilutive cash to scale a single product, look elsewhere: the EIC Accelerator (grant plus equity for one company) or the European Innovation Council Transition scheme fit that far better. Chips JU money is shared across a consortium and tied to a collaborative work plan, not handed to one team.
Pilot lines & competence centres
Five open-access pilot lines let companies prototype and validate advanced chips without building their own fab. NanoIC at imec (Leuven) pushes sub-2nm logic and is the largest at a combined €2.5bn (€700m EU, €700m national, the rest from ASML and industry partners). APECS, coordinated by Fraunhofer in Germany, handles advanced packaging and chiplets; FAMES (CEA-Leti, France) covers FD-SOI and emerging memory.
Open-access prototyping and small-volume manufacturing on cutting-edge process technology
A dedicated pilot line for advanced photonic integrated circuits, coordinated by ICFO in Barcelona with partners across eleven European countries. It offers cutting-edge platforms to move integrated-photonics processes from lab to industrial adoption.
Photonic chip prototyping and process transfer to industry
Focused on wide-band-gap semiconductor materials such as silicon carbide and gallium nitride, used in power electronics and radio-frequency applications. It builds specialised research infrastructure for the materials that make EVs, chargers and grid hardware more efficient.
Research and prototyping on SiC and GaN power and RF devices
A pan-European, cloud-based design platform coordinated by imec that gives SMEs, start-ups and fabless firms access to commercial EDA tools, IP libraries (including open-source) and a route to the pilot lines for fabrication, packaging and testing. It lowers the entry cost of designing a chip and is onboarding its first companies from 2026 through 2028.
Subsidised EDA-tool access, IP libraries and route-to-chip for fabless designers
A network of national Chips Competence Centres established across all 27 EU member states (plus Norway) to give local industry, SMEs and researchers a single front door to skills, design support and pilot-line access. They act as the on-the-ground delivery arm of the wider initiative.
Local training, expertise and signposting to Chips JU infrastructure
Annual collaborative calls in Electronic Components and Systems (ECS) fund consortia from low to high technology-readiness via Research and Innovation Actions (RIA) and Innovation Actions (IA). A 'Global' strand opens topics to international cooperation. EU money is matched by participating-state co-funding, so national eligibility rules apply.
Multi-partner R&D consortia in chips and electronic systems, co-funded by member states
Who wins — funded examples
The honest picture
The numbers are sobering, even if the Chips JU does not publish a headline success rate the way the EIC does. Individual 2026 calls are funded at €10-50 million each, and a single large pilot-line or design topic can absorb most of one call's budget — so only a handful of consortia win per topic, and competition concentrates on the big-name RTOs and tier-one chip firms. Realistically, selection rates sit in the single digits to ~20% depending on the call, and the bar is technical excellence judged by expert evaluators, not polish. The bigger trap is the co-funding model: this is NOT a near-full EU grant. The EU/Chips JU contribution is a minority slice — roughly 20% of costs for a large enterprise in an Innovation Action, up to around 35% for a non-profit — so the national co-funding from your own government is essential, not a bonus. Winning the Chips JU evaluation is necessary but not sufficient: you must ALSO secure that national co-funding, and national budgets are capped per country and can run out, so a technically excellent proposal can still go unfunded if your member state has no money left. Most rejections are not bad science; they are consortia that were too thin, mis-pitched the TRL, or assembled partners without genuine complementarity. If you are not already plugged into the European chip ecosystem (AENEAS, Inside, EPoSS industry associations), the realistic move is to join an existing consortium rather than lead your first one.
ECS Calls 2024 — submitted vs selected (Chips JU annual report)
| Call / topic | Submitted | Selected | Success rate |
|---|---|---|---|
| Global IA (2024-1, bottom-up) | 13 | 5 | 38% |
| IA focus topics (RISC-V, SDV) | 2 | 2 | 100% |
| Global RIA (2024-2, bottom-up) | 22 | 3 | 14% |
| RIA focus topic (greener manufacturing) | 1 | 1 | 100% |
| EU–Korea joint RIA (2024-3) | 15 | 4 | 27% |
| Total ECS calls 2024 | 53 | 15 | 28% |
⚠ The JU's own annual report concedes the success rate 'dropped significantly in 2024', blaming smaller budgets for the open bottom-up topics — the focus topics drew one or two bids each and sailed through. Two-stage calls gate hard: only proposals passing the Project Outline may submit a Full Project Proposal, and grant signature comes roughly 8 months after the final deadline.