Horizon Europe · JU-CHIPSHORIZON JU Research and Innovation Actions

RIA Resilience call reinforcing Europe's strength in 6G radio communication systems

Deadline16 September 2026
Total budget€20M
Grant size€1M–€20M
Expected grants1
Opens7 July 2026
Deadline modelsingle-stage
Call IDHORIZON-JU-CHIPS-2026-2-RIA

What this call funds

Expected Outcome

The proposals under this topic should address the design/specification and implementation/testing of the key microelectronics building blocks of an FR3 FEM paving the way towards their future integration into a complete integrated FEM system.

  • Progresses the State of the art to optimise the cost-performance trade off to serve the target ITU IMT 2030 specifications, notably for what concerns maximum data rate, user data rate, spectral efficiency, whilst enabling 50% mobile transmission system energy consumption;
  • Allows operational implementation of spectrum sharing with other spectrum users within the selected FR3 sub-band; • Enables large arrays integration for increased path loss compensation at FR3 frequencies with very compact, low power, high efficiency FEM integration;
  • Enables high bandwidth for carrier aggregation with broadband RF transceivers;
  • Enables SBFD (Sub-Band non overlapping Full-Duplex) for UL coverage extension (Rel.-19 5G-Advanced in 3GPP) with appropriate interference cancellation techniques;
  • Enables ISAC (Integrated Sensing and Communications) supporting monostatic as well as bistatic radar functionality, and addressing interference management, bandwidth, and potentially different waveforms (if appropriate) for communication and sensing functions;
  • Builds up on core technologies and IP blocks in view of their further in package integration for the various functionalities to be implemented, including as a minimum i) computing ii) RF iii) power generation technologies: iv) beam forming technologies; • Is based on semiconductor technology development supporting at least characterised models for RF, standard cell support for compute, interconnect and memory, and supported with relevant PDK and EDA support (analog/digital). • Enables base die development for implementation of the most critical functions and subsystem integration and paves the way towards their future complete integration enabling validation in real environment (outside of this project)
  • Enables FEM system integration with packaging; • Allows to progress European know-how in microelectronics domains where Europe is today less advanced, notably in the field of digital technologies, and with advances at least from the design perspective;
  • Paves the way towards the emergence of an alternative European ecosystem of technology suppliers for FEM modules as needed by EU vendors; • Stimulates related progresses in the field of design tools, notably for Process Design Kits (PDKs). • Extent to which the project results contribute to reinforce a European ecosystem of microelectronic suppliers for the telecom industry.
  • Stimulates related progresses in the field of design tools, notably for Process Design Kits (PDKs).

Collaboration with the relevant Pilot Lines is encouraged and a plan for further pre industrialisation of an integrated FEM SiP is part of the target outcomes.

Eligibility & conditions+

General conditions

1. Admissibility conditions: Proposal page limit and layout

Proposal page limits and layout: detailed in Part B of the Application Form, which you can access from the Call documents section on the Chips JU website's Call page

The following information are all described in the Appendix 7 of the Chips JU Workprogramme

2. Eligible countries

3. Other Eligibility Conditions

4. Financial and operational capacity and exclusion

5a. Evaluation and award: Award criteria, scoring and thresholds

5b. Evaluation and award: Submission and evaluation processes

5c. Evaluation and award: Indicative timeline for evaluation and grant agreement

6. Legal and financial set-up of the grants

Specific conditions

Please refer to the Appendix 7 of the Chips JU Workprogramme

Please refer to the calls documents section on the Chips JU website's Call page to view and download all required documents and templates.

Specific documents

2026 Guide for Applicants RIA_IA_FT-FPP

Evaluation Form Chips IA RIA FT-FPP

Template Application form Part B IA-RIA-FT FPP

Ownership Control Declaration form template

National Budgets Table template (xls)

General documents

Chips JU Multiannual Work Programme

Appendix 7 to the Work Programme - Electronic Components and Systems (ECS) - 2026

PAB decision on the evaluation and selection procedures related to Calls for Proposals

ECS Strategic Research and Innovation Agenda

Rules for legal entity validation, LEAR appointment, financial capacity and ownership control assessment

Annotated Model Grant Agreement for EU Funding Programmes 2021-2027

Application and evaluation forms and model grant agreement (MGA):

Guidance

HE Programme Guide

Call-specific instructions

Information on financial support to third parties (HE)

Information on clinical studies (HE)

Additional documents:

EU Financial Regulation 2024/2509

EU Grants AGA — Annotated Model Grant Agreement

Funding & Tenders Portal Online Manual

Funding & Tenders Portal Terms and Conditions

Funding & Tenders Portal Privacy Statement

Source: EU Funding & Tenders Portal · synced 2026-07-07